The invention pertains to an apparatus and technique for operating a computer system. In particular, apparatus and techniques for controlling address bus signals to improve performance are described.
FIG. 1 is a simplified block diagram of a parallel terminated bus system 10 between a core chip 2 and a cache chip 4. The drawing illustrates various uni-directional and bi-directional buses that carry strobe, address, data and command signals. In particular, an address strobe bus 6 is uni-directional and is used to transmit address strobe signals from the core 2 to the cache 4. An address bus 8, however, is bi-directional so that address information signals may be exchanged between the core 2 and cache 4 in either direction. The cache strobe bus 12, return information bus 14 and command bus 16 are all uni-directional, with the cache strobe and return information signals being transmitted from the cache to the core, and the command signals transmitted to the cache from the core. Each bus includes drivers 3 having an impedance Zo. and operable to drive signals to receivers 5. Each bus line is terminated at each receiver through a resistor R1 between the bus and the source power supply Voltage Vs, and through resistor R2 between the bus and ground. The bus therefore can be biased at a midpoint voltage when not driven by a driver. Such a configuration can make the rise and fall times of signals on the bus symmetrical, which is desirable in a source synchronous environment.
Any data exchange between drivers and receivers of two entities, such as between a processor and a memory device which may be on separate chips, is typically accomplished in a synchronous manner. That is, the chips have internal clocks that are sufficiently in alignment with each other so that data may be acquired on clock signal transitions. In addition, data exchanges may be accomplished source-synchronously, which means that the exchanges are based on strobe signal transitions that have been derived from a clock signal and are synchronized to their corresponding data.
A parallel termination protocol has been developed to ensure correct data signal operation for two or more bus agents across a large operating range. A parallel termination protocol may also be suitable for use with other entities that drive and receive data in a parallel environment. In an implementation, the parallel termination protocol requires that a signal must be driven at all times to prevent a signal from floating to an unspecified logic level. If certain signals were permitted to float, then the system would become unreliable. Such an occurrence may cause a fatal functional error in the system due to data transmission errors. To avoid such occurrences, the strobe signals could be uni-directional. Alternately, the parallel terminated protocol may specify that a bus agent designated as the default bus master will synchronously time the drive cut-off points to occur when another bus agent would drive a signal onto the bus, for example, to return data requested by the bus master. The parallel terminated protocol may also specify that the default bus master is to source-synchronously latch the value on the bus, turn on its drivers, and drive the latched value back onto the bus on the arrival of the last strobe signal for the reply sent by the cache. On certain occasions a prioritization of latched and outgoing data is accomplished to ensure correct operation.